FPGAs have become some of the most important drivers for development

FPGAs have become some of the most important drivers for development of leading edge semiconductor technology. The complexity of programmable devices, and their integration of diverse high-performance functions, provides excellent vehicles for testing new processes. It’s no accident that Intel has selected Achronix and Tabula, both makers of programmable devices, as the only partners that have been granted access to their 22 nm 3D Tri-Gate (FinFET) process. In February, Intel also announced an agreement with Altera, which will enable the company to manufacture FPGAs using their next-generation 14 nm Tri-Gate process.

In parallel with driving manufacturing, FPGA technology development must also include enhancements to design tools and flows. As vendors strive to make their devices more SoC- and ASIC-like, they are also adopting standards and collaborating with EDA companies to integrate their tools more seamlessly. These collaborations are producing great benefits for designers, as FPGA design methodologies are leading the way in areas that the EDA industry has long been promising new capabilities, such as in Electronic System Level (ESL) synthesis, IP integration and re-use, and higher-level tools for software/hardware co-design.

FPGA design methodologies have long integrated EDA point tools, such as simulation and PCB design, into FPGA vendor’s design platforms. Now, vendors such as Synopsys, with their Synplicity tools, and Xilinx with Vivado, are collaborating to build more complete integrated top-to-bottom flows. To address the greater complexity of FPGAs that may now contain up to two million equivalent logic cells, Synopsys has added Hierarchical Project Management (HPM) to Synplicity. HPM supports distributed design teams and parallel development, enabling partitioning of RTL and sharing of design debug tasks. Xilinx has adopted the industry-standard Synopsys Design Constraint (SDC) timing constraints (to replace Xilinx proprietary UDC) in a design flow that can be driven from standard Verilog HDL.

1.EASING IP INTEGRATION

Easier integration and re-use of semiconductor IP, especially when sourcing from multiple vendors, has been one of the greatest challenges to SoC designers and EDA tool flows. With the advent of higher capacity FPGA-based SoCs that utilize embedded ARM cores, those same challenges are now extended to the world of FPGA design....

2.INDUSTRY STANDARDS ENABLE HIGHER LEVELS OF ABSTRACTION

Building on their 2011 acquisition of AutoESL, Xilinx also says that they have expanded their C/C++ system-level design library for High-Level Synthesis (HLS) in the new Vivado release. Xilinx is targeting the growing market for embedded vision applications, following on their participation as a founding member of the Embedded Vision Alliance, with support for industry standard floating point math.h operations and real-time video processing functions. Designers of embedded vision systems will be able to utilize Vivado HLS integrated with the Open Source Computer Vision Library provided by the OpenCV organization. OpenCV is an open source BSD-licensed library of computer vision functions, which supports Windows,Linux, Mac, Android and Apple iOS operating systems. Vivado users will be able to develop embedded vision applications for the dual-core ARM Cortex A9 processor system in Zynq FPGAs, augmented with special-purpose hardware accelerators built in the programmable logic fabric....

3.THE FUTURE OF FPGAS

 Advances in FPGA tools and flows are good news for designers of programmable logic systems as well as ASIC and SoC designers. At a recent Synopsys User Group tutorial on the Synplicity-Vivado flow, the large majority of attendees were involved in FPGA prototyping, where the latest high-capacity FPGAs have become critical tools for design validation and signoff for complex SoCs. By utilizing the same design languages and standards for both ASIC and FPGA design, much duplication of effort can be eliminated and faster time-to-market will result.

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refer to :
http://dsp-fpga.com/articles/advances-in-eda-design-methodologies-led-by-next-generation-fpgas/

Simplifying the burden of AFE designs

The AFE is a critical, yet sometimes underappreciated component to a sensor system. The typical discrete approach of adding op-amps and filters, and trial-and-error soldering of resistors is not efficient and the cost of time in debugging and development easily outweighs the cost of adding an intelligent, MCU-based configurable AFE. But not all configurable AFEs are built the same. So, it is important to consider the flexibility and scalability of the AFE to support embedded types of sensors, and the intelligence to adjust “on the fly” or in the field. Simple, easy-to-use software tools can ease this process and can be embedded by even the non-analog experts on the team.

refer to:http://embedded-computing.com/articles/latest-afe-simplifies-interfacing-hundreds-sensors/#at_pco=cfd-1.0